1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof, and more particularly, to a semiconductor device including an insulating layer having a highly planarized surface and a method of manufacturing thereof.
2. Description of the Background Art
A structure of a conventional semiconductor device will first be described.
FIG. 15 is a sectional view of a conventional semiconductor device schematically showing a structure thereof. Referring to FIG. 15, an isolation oxide film 111 of approximately 300-800 nm in thickness is formed on the surface of a semiconductor substrate 110 of silicon. An element such as a MOSFET is provided in the region isolated by the isolation oxide film 111. This MOSFET is formed of impurity diffusion layers 114a and 114b serving as the source and drain, a gate oxide film 112, and a polycrystalline silicon film 101 serving as a gate.
The impurity diffusion layers 114a and 114b implementing the source and drain are formed at the surface of the semiconductor substrate 110, and include a portion of low concentration 114a and a portion of high concentration 114b. A gate oxide film 112 is formed on the surface of the semiconductor substrate 110 so as to span over the impurity diffusion layers 114a and 114b. A polycrystalline silicon film 101 implementing a gate is formed on the surface of the gate oxide film 112. A silicon oxide film 113 is formed on the surface of the polycrystalline silicon film 101. A sidewall 115a is formed at the sidewall of the polycrystalline silicon film 101 and the silicon oxide film 113.
A thin silicon oxide film or a nitride film 102 is formed all over the surface of the semiconductor substrate 110 having a MOSFET formed therein. A connection hole 118 is formed in the thin silicon oxide film/nitride film 102. A portion of the surface of the impurity diffusion layer 114b or the polycrystalline silicon film 101 is exposed in the connection hole 118. A polycrystalline silicon film 104a is formed on the surface of the thin silicon oxide film/nitride film 102 so as to be in contact with the exposing portion of the impurity diffusion layer 114b and the polycrystalline silicon film 101. A refractory metal thin film 104b is formed on the surface of the polycrystalline silicon film 104a. An interconnection layer is formed of the polycrystalline silicon film 104a and the refractory metal thin film 104b. On the entire surface of the thin silicon oxide film/nitride film 102 on which this interconnection layer is formed, an interlayer insulating layer 103 including impurities is formed to cover the interconnection layer. The interlayer insulating layer 103 is subjected to planarization. A connection hole 119 is formed in the interlayer insulating layer 103. A portion of the surface of the impurity diffusion region 114b not connected to the polycrystalline silicon film 104a is exposed in the connection hole 119. An interconnection layer 106 of an alloy of aluminum and copper is formed on the surface of the insulating layer 103 so as to form contact with the exposed portion of the impurity diffusion layer 114b.
A conventional semiconductor device has a structure as described in the foregoing.
Next, a method of manufacturing a conventional semiconductor device will be described hereinafter.
FIGS. 16-28 are sectional views of a conventional semiconductor device schematically showing the manufacturing steps thereof. Referring to FIG. 16, an isolation oxide film 111 of approximately 300-800 nm in film thickness is formed by local oxidation on the surface of a semiconductor substrate 110 of silicon.
Referring to FIG. 17, a gate oxide film 112 of 5-3 nm in film thickness is formed by thermal oxidation on an exposing region of the semiconductor substrate 110 not covered with the isolation oxide film 111. Then, a polycrystalline silicon film 101 including phosphorus and arsenic and a silicon oxide film 113 are formed on the surface of the semiconductor substrate 110 by chemical vapor deposition. The gate oxide film 112, the polycrystalline silicon film 101, and the silicon oxide film 113 are patterned by photolithography and RIE.
Referring to FIG. 18, impurity ions are implanted to the semiconductor substrate 110 using the polycrystalline silicon film 101, the silicon oxide film 113, and the isolation oxide film 111 as a mask. By this ion implantation, an impurity diffusion layer 114a is formed on the exposed surface of the semiconductor substrate 110.
Referring to FIG. 19, a silicon oxide film 115 is formed to a thickness of 50-300 nm on the surface of the semiconductor substrate 110 by chemical vapor deposition.
Referring to FIG. 20, the silicon oxide film 115 is etched by RIE to form a sidewall 115a at the sidewall of the polycrystalline silicon film 101 and the silicon oxide film 113. Impurity ions are implanted into the semiconductor substrate 110 using the sidewall 115a, the silicon oxide film 113, and the isolation oxide film 111 as a mask to form an impurity diffusion layer 114b. A two layered structure of a portion of high impurity concentration and a portion of low impurity concentration is formed by these impurity diffusion layers 114b and 114a. By the formation of the impurity diffusion layers, a MOS transistor is implemented of impurity diffusion layers 114a, 114b, a gate oxide film 112, and a polycrystalline silicon film 101.
Referring to FIG. 21, a thin silicon oxide film or a nitride film 102 is deposited so as to cover an element such as a MOS transistor formed on the surface of the semiconductor substrate 110.
Referring to FIG. 22, a connection hole 118 is formed in the thin silicon oxide film/nitride film 102 by photolithography and RIE. A portion of the surface of the impurity diffusion layer 114b or the polycrystalline silicon film 101 is exposed in the connection hole 118. In the exposure process of the polycrystalline silicon film 101, the silicon oxide film 113 is also etched.
Referring to FIG. 23, a polycrystalline silicon film 104a and a refractory metal thin film 104b are formed all over the surface of the thin silicon oxide film/nitride film 102 by chemical vapor deposition. The polycrystalline silicon film 104a is electrically connected to the impurity diffusion layer 114b or the polycrystalline silicon film 101 via the connection hole 118.
Referring to FIG. 24, the polycrystalline silicon film 104a and the refractory metal thin film 104b are patterned by photolithography and RIE. By this patterning process, an interconnection layer constituted by the polycrystalline silicon film 104a and the refractory metal thin film 104b is formed.
Referring to FIG. 25, an oxide film 103a including impurities is deposited on the surface of the semiconductor substrate 110 so as to cover the interconnection layer formed of the polycrystalline silicon film 104a and the refractory metal thin film 104b.
Referring to FIG. 26, the oxide film 103a including impurities is subjected to thermal treatment at a temperature of 800.degree. C.-1000.degree. C. for planarization. Following the thermal treatment, the oxide film 103a including impurities is reduced in film thickness by an overall etching. A thin oxide film or a nitride film is deposited on the surface of the oxide film 103a including impurities. Thus, an interlayer insulating layer 103 is obtained.
Referring to FIG. 27, a connection hole 119 is formed in the interlayer insulating layer 103 by photolithography and RIE. The connection hole 119 is formed to reach the impurity diffusion layer 114b that is not electrically connected to the polycrystalline silicon film 104a.
Referring to FIG. 28, an aluminum-copper alloy film is deposited on the surface of the interlayer insulating layer 103 by sputtering. By patterning this aluminum-copper alloy film by photolithography and RIE, an interconnection layer 106 is formed. This interconnection layer 106 is electrically connected to the impurity diffusion layer 114b via the connection hole 119.
A conventional semiconductor device is formed as described in the foregoing.
Because a conventional semiconductor device was formed as described above, the surface of the interlayer insulating layer 103 was insufficient in planarization. An interlayer insulating layer 103 having a surface lacking planarization will generate problems as set forth in the following.
FIG. 29 is a sectional diagram schematically showing a state of exposing a resist. Referring to FIG. 29, a resist 202 is applied on the surface of an underlying layer 201. The resist 202 is patterned to a desired configuration using a mask 203. In this patterning process, the light of exposure is introduced in a direction indicated by the arrow A only into a region 202a that should be exposed defined by the mask 203. However, the presence of a stepped portion in the underlying layer 201 will cause the light of exposure to be reflected in the direction indicated by arrow B. This reflected light in the direction of arrow B will expose a region 202b which should not be actually exposed. This means that it is difficult to expose the resist 202 to a desired configuration if there is a stepped portion in the underlying layer 201. Thus, it will be difficult to pattern the resist 202 properly to a desired configuration.
FIG. 30 is a sectional diagram schematically showing the optimum focusing position in exposing a resist. Referring to FIG. 30, a resist 202 is applied on the surface of an underlying layer 201. A stepped portion in the underlying layer 201 will result in a resist 202 differing in thickness according to the portion thereof. A difference in thickness will mean that the optimum focusing position of the light of exposure for exposing the resist 202 will also differ. More specifically, the optimum focusing position of the light of exposure at the respective positions of C and D is c and d, respectively, as shown in FIG. 30. If exposure is carried out conforming to the focus at position C, the pattern at position D will be degraded in configuration. Conversely, if exposure is carried out conforming to the focus at position D, the pattern at position C is degraded in configuration as shown in FIG. 32. It is therefore difficult to properly pattern the resist 202 in a desired configuration.
As described above, the resist 202 cannot be patterned to a desired configuration if there is a stepped portion in the underlying layer 201. If etching is carried out using such a resist of unsatisfactory configuration as a mask, the dimension of the finished product will differ from the design dimension. Such an offset in the finished dimension will be a fatal disadvantage in the attempt to reduce the size of semiconductor devices, with difficulty in the formation of patterns of connection holes and metal interconnection layers.
There is also a problem which will be described hereinafter in the case of filling a connection hole with a plug if the surface of the interlayer insulating layer of FIG. 28 is not sufficient in planarization.
FIGS. 33 and 34 are a sectional view and a plan view, respectively, of a semiconductor device schematically showing a problem encountered by filling the connection hole with a plug. Referring to FIGS. 33 and 34, a plug 202 is formed in a connection hole 201. An upper conductive layer 204 is electrically connected to a lower conductive layer 203 by means of the plug 202. This plug 202 is obtained by etching a conductive layer deposited all over the surface of the insulating layer 205. An insufficient planarization of the surface of the insulating layer 205 will result in a residue 202a at the stepped portion on the surface of the insulating layer 205 at the time of plug formation. There is a possibility of other interconnection layers 206a and 206b being short circuited by this residue 202a, as shown in FIG. 34. There was a problem of degradation in electrical reliability such as shorting of the interconnection layers due to generation of a residue in the stepped portion if planarization was not sufficient in the surface of the interlayer insulating layer 103 shown in FIG. 28.